Multiprocessor Scheduling

Chapter 10 puts several CPUs, each with its own cache, in front of the scheduler built in Chapters 7–9. This tool follows the three issues a single-CPU scheduler never had to face — cache coherence, synchronization and cache affinity — then compares the two classic ways to organize run queues across CPUs: one shared queue (SQMS) and one queue per CPU (MQMS), including what MQMS has to do about the load imbalance it creates.

Why one CPU's assumptions break with several

  • Every CPU on a multicore chip has its own private cache to avoid hitting main memory on every access.
  • Caching keeps single-CPU scheduling cheap — but now the same memory location can have multiple, disagreeing copies, one per CPU cache.
  • This is the cache coherence problem: hardware has to make sure every CPU eventually sees the same value for the same address.

Watch a stale read happen

CPU 1 caches a value, then CPU 2 changes it. Step through with and without a coherence protocol.

Scenario
CPU 1
cache: empty
CPU 2
cache: empty
Memory: D = 50
Press Next to start, or Play to animate.

    Coherence is solved in hardware, not by the scheduler: protocols like bus snooping watch every write and invalidate or update stale copies so all CPUs agree on one value per address.